The fabrication of semiconductor devices involves forming electronic components in and on semiconductor substrates, such as silicon wafers. These electronic components may include one or more conductive layers, one or more insulation layers, and doped regions formed by implanting various dopants into portions of a semiconductor substrate to achieve specific electrical properties. Semiconductor devices include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the semiconductor devices to form integrated circuits.
The semiconductor fabrication process is broken down into two parts, the front end of line (FEOL) process and the back end of line (BEOL) process. The FEOL process is the first portion of the semiconductor fabrication process. Typically, during the FEOL process, the individual devices, such as the transistors, capacitors and resistors, desired for the semiconductor device, are patterned in the semiconductor. The FEOL process generally covers everything up to, but not including, the deposition of the metal interconnect layers of the semiconductor device.
The BEOL process is the second portion of the semiconductor fabrication process. After the FEOL process, there is a wafer with isolated transistors (without any wires). The wafer then moves into the BEOL process, where contact pads, interconnect wires, vias, and dielectric structures are formed.
As stated above, individual devices, such as field-effect transistors, are typically patterned in the semiconductor during the FEOL process. Field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs), are a commonly used semiconductor device. Generally, a FET has three terminals, i.e., a gate (or gate stack), a source region, and a drain region. In some instances, the body of the semiconductor may be considered a fourth terminal. The gate stack is a structure used to control output current, i.e., flow of carriers in the channel portion of a FET, through electrical or magnetic fields. The channel portion of the substrate is the region between the source region and the drain region of a semiconductor device that becomes conductive when the semiconductor device is turned on. The source region is a doped region in the semiconductor device from which majority carriers are flowing into the channel portion. The drain region is a doped region in the semiconductor device located at the end of the channel portion, in which carriers are flowing into, from the source region via the channel portion, and out of the semiconductor device through the drain region. A conductive plug, or contact, is electrically coupled to each terminal. One contact is made to the source region, one contact is made to the drain region, and one contact is made to the gate.